Any limitation on using LVDS?
41583: 02/04/02: Re: powerpc in virtex2pro 41628: 02/04/03: Re: powerpc in virtex2pro 41645: 02/04/04: Re: powerpc in virtex2pro 41666: 02/04/04: Re: powerpc in virtex2pro 41798: 02/04/08: Re: Variable phase-shift 41820: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot 41824: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot 42112: 02/04/16: Re: Using SRL16E Xilinx primitive. 42162: 02/04/17: Re: FPGA Timing Problem 42168: 02/04/17: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in 42209: 02/04/18: Re: GND Outputs being optimized out using FPGA Express 3.6.