configuration with Altera EPC16?
62383: 03/10/28: Re: Sort of Running Quartus II on SuSE Linux 8.1 Charles F. Shelor: 1255: 95/05/23: Yet Another Seminar Announcement 1370: 95/06/08: (no subject) 1371: 95/06/08: Virtually FREE VHDL/ASIC seminars 1922: 95/09/20: Re: REPOST: Design Contest Write-up ( was “Jury Verdict + Test Benches” ) 7666: 97/10/01: Logic Synthesis Methodology shortcourse 8274: 97/12/04: VHDL -> XNF via Synopsys 8797: 98/01/27: Re: comparing asic gates with gates in FPGA’s 8818: 98/01/28: Re: comparing asic gates with gates in FPGA’s 14942: 99/02/26: wanted: info about Fast Ethernet cores Charles Flaig: 45: 94/08/03: Re: Welcome new XILINX users Charles Gardiner: 3148: 96/04/14: Crosspoint Solutions 25462: 00/09/12: Accessing internal signals and ports for writing to a file using 31290: 01/05/17: Re: Digital PLL (DPLL) design help 31637: 01/06/01: Re: Help in FIFO design 52873: 03/02/25: AHB 54745: 03/04/17: Re: open SOC-bus system required!