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Why PLL and not DCM for V5?

April 26, 2017DCM PLL V5

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Why PLL and not DCM for V5?

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121331: 07/07/02: Can I use chipscoe to look at V5 GTPoutputs 121760: 07/07/12: CML output swing for V5 121778: 07/07/12: Re: CML output swing for V5 121779: 07/07/12: Re: CML output swing for V5 121801: 07/07/13: Re: CML output swing for V5 121830: 07/07/13: Re: CML output swing for V5 121840: 07/07/13: Re: CML output swing for V5 121866: 07/07/13: Re: CML output swing for V5 122154: 07/07/20: Running Virtex5 GTP at lower data rate 122156: 07/07/20: Re: Running Virtex5 GTP at lower data rate 122295: 07/07/25: Re: Running Virtex5 GTP at lower data rate 122342: 07/07/25: Timing simulation 122348: 07/07/25: Re: Timing simulation 122358: 07/07/25: Re: Timing simulation 122429: 07/07/27: Re: Timing simulation 122741: 07/08/05: Single Ended signal in sync with V5 GTP 122744: 07/08/05: Re: Single Ended signal in sync with V5 GTP 122768: 07/08/06: Re: Single Ended signal in sync with V5 GTP 122798: 07/08/07: Re: Single Ended signal in sync with V5 GTP 123215: 07/08/20: Voltage translation que