whether the described model reflects the intended behavior?
A tool called a simulator is used to simulate the model in order to verify that the description is working as intended. (It is usually not the case that the model is correct when first described.) Note that at this stage the simulator only simulates the VHDL model and not the real circuit. I.e., the behavior of the model and the hardware that is finally generated from it may differ in ways that may be significant. (There are other tools and methods to detect such problems; see below). In addition to the VHDL model of the circuit to be developed, a “testbench” should also be coded. The purpose of the testbench is to provide an environment that generates appropriate input to the model and that also checks its output. Unlike the circuit model, the testbench does not have to be synthesizable. Hence, all language features can be used to describe it (e.g., file read and write operations to log input to and output of the circuit). While some FPGA vendors provide “home grown” simulators along
