to both read and write?
Texture read operations are routed through a cache structure to allow efficient exploitation of reference locality. Read operations also factor into shader thread scheduling as read operations that miss the cache will block the thread and cause other ready threads to run while waiting for the read to memory to complete. Writes are routed through different logic that does some amount of buffering to maximize the efficieny of writes. Memory reads and writes are block-oriented, with each transaction typically involving 32 bytes per memory chip, so maximizing the number valid bytes in a transaction improves system performance. Finally, supporting read-modify-write operations for depth buffering or blending requires careful pipelining and scheduling of memory operations to maximize efficiency of the memory system. In current GPUs the subsystems for texture reading and pixel writing are independent and meet at the shared memory controller. Therefore trying to concurrently read and write to t
